photodiode arrays with ampli ? er photodiode array combined with signal processing ic s8866-64/-128 www.hamamatsu.com structure parameter symbol * 1 s8866-64 s8866-128 unit element pitch p 1.6 0.8 mm element diffusion width w 1.5 0.7 mm element height h 1.6 0.8 mm number of elements - 64 128 - effective photosensitive area length - 102.4 102.4 mm board material - ceramic - * 1: refer to following ? gure. enlarged drawing of photosensitive area kmpdc0072ea the s8866-64 and s8866-128 are si photodiode arrays combined with a signal processing ic chip. the signal processing ic chip is formed by cmos process and incorporates a timing generator, shift register, charge ampli ? er array, clamp circuit and hold circuit, making the external circuit con ? guration simple. for x-ray detection applications, types (s8866-64g-02, s8866- 128g-02) with phosphor sheet af ? xed on the photosensitive area are also available. 1 h w p photodiode features applications large element pitch: 2 types available s8866-64: 1.6 mm pitch 64 ch s8866-128: 0.8 mm pitch 128 ch 5 v power supply operation simultaneous integration by using a charge ampli ? er array sequential readout with a shift register (data rate: 500 khz max.) low dark current due to zero-bias photodiode operation integrated clamp circuit allows low noise and wide dynamic range integrated timing generator allows operation at two different pulse timings long and narrow line sensors
photodiode arrays with ampli ? er s8866-64/-128 absolute maximum ratings parameter symbol value unit supply voltage vdd -0.3 to +6 v reference voltage vref -0.3 to +6 v photodiode voltage vpd -0.3 to +6 v gain selection terminal voltage vgain -0.3 to +6 v master/slave selection voltage vms -0.3 to +6 v clock pulse voltage v(clk) -0.3 to +6 v reset pulse voltage v(reset) -0.3 to +6 v external start pulse voltage v(extsp) -0.3 to +6 v operating temperature * 2 topr -5 to +60 c storage temperature tstg -10 to +70 c * 2: no condensation 2 recommended terminal voltage electrical characteristics [ta=25 c, vdd=5 v, v(clk)=v(reset)=5 v] parameter symbol min. typ. max. unit supply voltage vdd 4.75 5 5.25 v reference voltage vref 4 4.5 4.6 v photodiode voltage vpd - vref - v gain selection terminal voltage high gain vgain vdd - 0.25 vdd vdd + 0.25 v low gain 0 - 0.4 v master/slave selection voltage high level * 3 vms vdd - 0.25 vdd vdd + 0.25 v low level * 4 0-0.4v clock pulse voltage high level v(clk) 3.3 vdd vdd + 0.25 v low level 0 - 0.4 v reset pulse voltage high level v(reset) 3.3 vdd vdd + 0.25 v low level 0 - 0.4 v external start pulse voltage high level v(extsp) vdd - 0.25 vdd vdd + 0.25 v low level 0 - 0.4 v * 3: parallel * 4: serial at 2nd or later stages parameter symbol s8866-64 s8866-128 unit min. typ. max. min. typ. max. clock pulse frequency * 5 f(clk) 40 - 2000 40 - 2000 khz line rate lr - 7800 - - 3900 - lines/s output impedance zo - 3 - - 3 - k power consumption p - 100 - - 180 - mw charge amp feedback capacitance high gain cf -0.5- -0.5- pf low gain - 1 - - 1 - * 5: video data rate is 1/4 of clock pulse frequency f(clk).
photodiode arrays with ampli ? er s8866-64/-128 output waveform of one element 3 electrical and optical characteristics [ta=25 c, vdd=5 v, v (clk)=v (reset)=5 v, vgain=5 v (high gain), 0 v (low gain)] parameter symbol s8866-64 s8866-128 unit min. typ. max. min. typ. max. spectral response range 300 to 1000 300 to 1000 nm peak sensitivity wavelength p - 720 - - 720 - nm dark output voltage * 6 high gain vd - 0.01 0.2 - 0.01 0.2 mv low gain - 0.005 0.1 - 0.005 0.1 saturation output voltage vsat 3 3.5 - 3 3.5 - v saturation exposure * 7 high gain esat - 0.2 0.25 - 0.8 1.0 m lx s low gain - 0.4 0.5 - 1.6 2.0 photo sensitivity high gain s 14400 18000 - 3520 4400 - v/ lx s low gain 7200 9000 - 1760 2200 - photo response non-uniformity * 8 prnu - - 10 -- 10 % noise * 9 high gain n - 2.0 3.0 - 1.3 2.0 mvrms low gain - 1.1 1.7 - 0.7 1.1 output offset voltage * 10 vos - vref - - vref - v * 6: integration time ts=1 ms * 7: measured with a 2856 k tungsten lamp. * 8: when the photodiode array is exposed to uniform light which is 50% of the saturation exposure, the photo response non-unifor mity (prnu) is de ? ned as follows: prnu = x/x 100 [%] x: average output of all elements, x: difference between x and the maximum or minimum output, whichever is larger. * 9: measured with a video data rate of 50 khz and ts=1 ms in dark state. * 10: video output is negative-going output with respect to the output offset voltage. output offset voltage vref=4.5 v typ. saturation output voltage vsat=3.5 v typ. gnd gnd gnd 200 ns/div. 1 v/div. 10 v/div. trigger clk saturation state dark state 1 v typ.
photodiode arrays with ampli ? er s8866-64/-128 block diagram kmpdc0153ea 4 1 4 reset extsp vms vdd gnd clk vref vgain vpd 2 10 11 12 5 6 7 timing generator shift register hold circuit charge amp array photodiode array 3trig 8eos 9video 12345 n-1n
photodiode arrays with ampli ? er s8866-64/-128 spectral response (measurement example) output offset voltage vs. ambient temperature (measurement example) dark output voltage vs. ambient temperature (measurement example) 0.5 0.4 0.3 0.2 0.1 0 200 400 600 800 wavelength (nm) 1000 1200 photo sensitivity (a/w) (ta=25 c) 0 4.495 4.505 4.504 4.503 4.502 4.501 4.500 4.499 4.498 4.497 4.496 10 20 30 40 50 60 ambient temperature (c) output offset voltage (v) 0 0.001 (ts=1000 ms) 1 0.1 0.01 10 20 30 40 50 60 ambient temperature (c) dark output voltage (v) kmpdb0275ea kmpdb0288ea kmpdb0289ea 5
photodiode arrays with ampli ? er s8866-64/-128 timing chart 1 2 3 1 2 3 4 5 14 15 16 17 video output period clk reset video trig eos tf(clk) tf(reset) tpw(clk1) t1 t2 tpw(reset1) tpw(reset2) tr(clk) tpw(reset2) 18 19 20 12n-1n tr(reset) tpw(reset1) 20 clocks 8 clocks 8 clocks integration time kmpdc0278ea parameter symbol min. typ. max. unit clock pulse width tpw(clk) 500 - 25000 ns clock pulse rise/fall times tr(clk), tf(clk) 0 20 30 ns reset pulse width 1 tpw(reset1) 21 - - clk reset pulse width 2 tpw(reset2) 20 - - clk reset pulse rise/fall times tr(reset), tf(reset) 0 20 30 ns clock pulse-reset pulse timing 1 t1 -20 0 20 ns clock pulse-reset pulse timing 2 t2 -20 0 20 ns 1. the internal timing circuit starts operation at the falling edge of clk immediately after a reset pulse goes low. 2. when the falling edge of each clk is counted as "1 clock", the video signal of the 1st channel appears between "18.5 clocks and 20 clocks". subsequent video signals appear every 4 clocks. 3. to obtain video signals, extend the high period 3 clocks from the falling edge of clk immediately after the reset pulse goes low, to a 20 clock period. 4. the trigger pulse for the 1st channel rises at a timing of 19.5 clocks and then rises every 4 clocks. the rising edge of eac h trigger pulse is the recommended timing for data acquisition. 5. signal charge integration time equals the high period of a reset pulse. however, the charge integration does not start at th e rise of a reset pulse but starts at the 8th clock after the rise of the reset pulse and ends at the 8th clock after the fall of the reset pulse. after the reset pulse next changes from high to low, signals integrated within this period are sequentially read out as time- series signals by the shift register operation. the rise and fall of a reset pulse must be synchronized with the rise of a clk pulse, but the rise of a reset pulse must be set outside the video output period. one cycle of reset pulses cannot be set shorter than the time equal to "36.5 + 4 n (number of elements)" clocks. 6. the video signal after an eos signal output becomes a high impedance state, and the video output will be inde ? nite. 6 s8866-64
photodiode arrays with ampli ? er s8866-64/-128 1 2 3 1 2 3 4 5 14 15 16 17 video output period clk reset video trig eos tf(clk) tf(reset) tpw(clk) t1 t2 tpw(reset1) tpw(reset2) tr(clk) tpw(reset2) 18 19 20 12n-1n tr(reset) 8 clocks 8 clocks integration time tpw(reset1) kmpdc0289ea parameter symbol min. typ. max. unit clock pulse width tpw(clk) 500 - 25000 ns clock pulse rise/fall times tr(clk), tf(clk) 0 20 30 ns reset pulse width 1 tpw(reset1) 21 - - clk reset pulse width 2 tpw(reset2) 20 - - clk reset pulse rise/fall times tr(reset), tf(reset) 0 20 30 ns clock pulse-reset pulse timing 1 t1 -20 0 20 ns clock pulse-reset pulse timing 2 t2 -20 0 20 ns 1. the internal timing circuit starts operation at the falling edge of clk immediately after a reset pulse goes low. 2. when the falling edge of each clk is counted as "1 clock", the video signal of the 1st channel appears between "18.5 clocks and 20 clocks". subsequent video signals appear every 4 clocks. 3. the trigger pulse for the 1st channel rises at a timing of 19.5 clocks and then rises every 4 clocks. the rising edge of eac h trigger pulse is the recommended timing for data acquisition. 4. signal charge integration time equals the high period of a reset pulse. however, the charge integration does not start at th e rise of a reset pulse but starts at the 8th clock after the rise of the reset pulse and ends at the 8th clock after the fall of the reset pulse. after the reset pulse next changes from high to low, signals integrated within this period are sequentially read out as time-series signals by the shift register operation. the rise and fall of a reset pulse must be synchronized with the rise of a clk pulse, but the rise of a reset pulse must be set outside the video output period. one cycle of reset pulses cannot be set short er than the time equal to "16.5 + 4 n (number of elements)" clocks. 5. the video signal after an eos signal output becomes a high impedance state, and the video output will be inde ? nite. 7 s8866-128
8 photodiode arrays with ampli ? er s8866-64/-128 direction of scan 0.25 0.5 10 3.5 0.5 1.0 0.1 1.5 max. 12 0.5 110 1.1 25.4 12 silicon resin signal processing ic chip photodiode 1 ch photosensitive area * length from the bottom of the board to the center of photosensitive area board: ceramic 1 102.4 p2.54 5 = 12.7 p2.54 5 = 12.7 a * s8866-64 type no. a 3.2 s8866-128 3.0 dimensional outline (unit: mm) kmpda0225eb gain selection terminal voltage setting vdd: high gain (cf=0.5 pf) gnd: low gain (cf=1 pf) pin connections pin no. symbol name note 1 reset reset pulse pulse input 2 clk clock pulse pulse input 3 trig trigger pulse positive-going pulse output 4 extsp external start pulse pulse input 5 vms master/slave selection supply voltage voltage input 6 vdd supply voltage voltage input 7 gnd ground 8 eos end of scan negative-going pulse output 9 video video output negative-going output with respect to vref 10 vref reference voltage voltage input 11 vgain gain selection terminal voltage voltage input 12 vpd photodiode voltage voltage input
9 photodiode arrays with ampli ? er s8866-64/-128 [figure 1] connection example (parallel readout) readout circuit check that pulse signals meet the required pulse conditions before supplying them to the input terminals. video output should be ampli ? ed by an operational ampli ? er that is connected close to the sensor. setting for each readout method set to a in the table below in most cases. to serially read out signals from two or more sensors linearly connected, set the 1st sensor to a and the 2nd or later sensors to b. the clk and reset pulses should be shared with each sensor and the video output terminal of each sensor connected together. setting readout method vms extsp a all stages of parallel readout, serial readout at 1st sensor vdd vdd b serial readout at 2nd and later sensors gnd preceding sensor eos should be input vgain +4.5 v eos +5 v 10 f0.1 f trig clk reset video - + high impedance amplifier vpd vgain vref video eos gnd vdd vms extsp trig clk reset 12 11 10 9 8 7 6 5 4 3 2 1 kmpdc0288ea
cat. no. kmpd1104e02 may 2011 dn www.hamamatsu.com hamamatsu photonics k.k., solid state division 1126-1 ichino-cho, higashi-ku, hamamatsu city, 435-8558 japan, telephone: (81) 53-434-3311, fax: (81) 53-434-5184 u.s.a.: hamamatsu corporation: 360 foothill road, p.o.box 6910, bridgewater, n.j. 08807-0910, u.s.a., telephone: (1) 908-231-0 960, fax: (1) 908-231-1218 germany: hamamatsu photonics deutschland gmbh: arzbergerstr. 10, d-82211 herrsching am ammersee, germany, telephone: (49) 8152- 375-0, fax: (49) 8152-265-8 france: hamamatsu photonics france s.a.r.l.: 19, rue du saule trapu, parc du moulin de massy, 91882 massy cedex, france, teleph one: 33-(1) 69 53 71 00, fax: 33-(1) 69 53 71 10 united kingdom: hamamatsu photonics uk limited: 2 howard court, 10 tewin road, welwyn garden city, hertfordshire al7 1bw, unit ed kingdom, telephone: (44) 1707-294888, fax: (44) 1707-325777 north europe: hamamatsu photonics norden ab: smidesv?gen 12, se-171 41 solna, sweden, telephone: (46) 8-509-031-00, fax: (46) 8 -509-031-01 italy: hamamatsu photonics italia s.r.l.: strada della moia, 1 int. 6, 20020 arese, (milano), italy, telephone: (39) 02-935-81- 733, fax: (39) 02-935-81-741 information described in this material is current as of may, 2011. product specifications are subject to change without prior n otice due to improvements or other reasons. before assembly into final products, please contact us for the delivery specification sheet to check the latest information. type numbers of products listed in the delivery specification sheets or supplied as samples may have a suffix "(x)" which means preliminary specifications or a suffix "(z)" which means developmental specifications. the product warranty is valid for one year after delivery and is limited to product repair or replacement for defects discovere d and reported to us within that one year period. however, even if within the warranty period we accept absolutely no liability for any loss caused by natural d isasters or improper product use. copying or reprinting the contents described in this material in whole or in part is prohibited without our prior permission. photodiode arrays with ampli ? er s8866-64/-128 precautions for use (1) the signal processing ic chip is protected against static electricity. however, in order to prevent possible damage to the ic chip, take electrostatic countermeasures such as grounding yourself, as well as workbench and tools. also protect the ic chip from su rge voltages from peripheral equipment. (2) gold wires for wire bonding are very thin, so they easily break if subjected to mechanical stress. the signal processing ic chip, wire bonding section and photodiode array chip are covered with resin for protection. however, never touch these portions. excessive force, if applied, may break the wires or cause malfunction. blow air to remove dust or debris if it gets on the protective resin. never wash them with solvent. signals may not be obtained if dust or debris is left or a scratch is made on the protective resin, or the signal processing ic chip or photodiode array chip is nicked. (3) the photodiode array characteristics may deteriorate when operated at high humidity, so put it in a hermetically sealed enclosu re or case. when installing the photodiode array on a board, be careful not to cause the board to warp. 10
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